The present invention generally relates to semiconductor devices having dielectric layers. In particular, the present invention relates to a precision high-K intergate dielectric layer and a method of forming the same.
A conventional floating gate FLASH memory device includes a FLASH memory cell characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric, a floating gate, an intergate dielectric layer and a control gate. The gate dielectric of silicon dioxide (SiO2 gate dielectric), for example, is formed on the semiconductor substrate. The floating gate (sometimes referred as the xe2x80x9ccharge storing layerxe2x80x9d) of polysilicon, for example, is formed on the gate dielectric. The intergate dielectric layer (e.g., layers of SiO2, silicon nitride (xe2x80x9cnitridexe2x80x9d) and SiO2) is formed on the floating gate. The control gate of polysilicon, for example, is formed on the intergate dielectric layer. The floating gate formed on the SiO2 gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and drain are formed by dopant impurities introduced into the semiconductor substrate.
Generally speaking, a FLASH memory cell is programmed by inducing hot electron injection from a portion of the semiconductor substrate, such as the channel section near the drain, to the floating gate. Electron injection introduces negative charge into the floating gate. The injection mechanism can be induced by grounding the source and a bulk portion of the semiconductor substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates in the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a FLASH memory cell is programmed.
The act of discharging the floating gate of a FLASH memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase or negative gate erase), or between the floating gate and the semiconductor substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source and a 0 V to the control gate and the semiconductor substrate while floating the drain of the respective FLASH memory cell.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FLASH memory cells, having feature sizes as small as possible. Many present processes employ features, such as floating gates and interconnects, which have less than a 0.18 xcexcm critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area
As semiconductor device feature sizes decrease, the thicknesses of the SiO2 layers in the intergate dielectric layer decrease as well. This decrease in SiO2 layer thickness is driven in part by the demands of overall device scaling. As floating gate widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO2 layer thickness, operating voltage, depletion width, and junction depth, for example.
As a result of the continuing decrease in feature size, SiO2 layer thickness has been reduced so much that SiO2 layers of the intergate dielectric layer are approaching thicknesses on the order of ten angstroms (xc3x85) (1 nm). Unfortunately, thin SiO2 layers may break down when subjected to an electric field, particularly SiO2 layers less than 50 angstroms (xc3x85) (10 nm) thick of the intergate dielectric layer. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such thin SiO2 layers by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the control gate and the floating gate, adversely affecting the operability of the device. For example, the leakage current increases exponentially for about a two-fold decrease in thickness of a SiO2 layer. The exponential increase in the SiO2 layer leakage current significantly affects the operation of semiconductor devices, particularly with regard to standby power, dissipation, reliability and lifetime.
Another disadvantage of thin SiO2 layers is that some electrons may become entrapped within the SiO2 layers by, e.g., dangling bonds. As a result, a net negative charge density may form in the SiO2 layers of the intergate dielectric layer. As the trapped charge accumulates with time, the threshold voltage VT may shift from its design specification.
Still another disadvantage of thin SiO2 layers is that a breakdown of the SiO2 layers may also occur at even lower values of gate voltage, as a result of defects in the SiO2 layers. Such defects are unfortunately prevalent in relatively thin SiO2 layers. For example, a thin SiO2 layer often contains pinholes and/or localized voids due to unevenness at which the SiO2 layer grows on a less than perfect silicon lattice or is deposited on the nitride layer.
Additionally, the deposition of thin SiO2 layers is more difficult to control due to inherent limitations of the deposition process. As devices are produced having layers with thicknesses on the order of a few monolayers, the thickness variation of these layers over a 200-mm or 300-mm silicon wafer is of substantial concern. A variation in thickness of only 1.0 angstrom (xc3x85) (0.1 nm) could result in changes in the device operating conditions. For example, the electron or hole mobility or the device transconductance may be affected. Additionally, variations in layer thickness make it extremely difficult to maintain device tolerances. Further, the layer thicknesses not only vary within a wafer, but also vary from lot to lot which affects the manufacturing of wafers.
Therefore, there exists a strong need in the art for a dielectric layer which incorporates a high-K dielectric material which is formed with precise uniformity, thickness, abrupt atomic interfaces, etc., in order for semiconductor devices to be further scaled without reducing the data retention of the finished device. Additionally, the relatively high-K material increases the electric field in the intergate dielectric layer such that in an erase mode electrons in the charge storing layer will tunnel through the relatively low-K material of the SiO2 gate dielectric.
One promising approach for maintaining the capacitance and thickness of the intergate dielectric layer may be to increase the permittivity of a layer(s) in order to xe2x80x9creducexe2x80x9d an electrical equivalent thickness of the layer(s) of the intergate dielectric layer. Permittivity, ∈, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, ∈0. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
K=∈/∈0
While SiO2 (sometimes simply referred to as xe2x80x9coxidexe2x80x9d) has a dielectric constant of approximately 3.9, other materials have higher K values. Silicon nitride (xe2x80x9cnitridexe2x80x9d), for example, has a K of about 6 to 9 (depending on formation conditions) and aluminum oxide (Al2O3) has a K of about 9 to 10. Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta2O5), barium strontium titanate (xe2x80x9cBSTxe2x80x9d), and lead zirconate titanate (xe2x80x9cPZTxe2x80x9d).
For example, using a dielectric material with a higher K for one or more of the layers of the intergate dielectric layer would allow a high capacitance and an electrical equivalent thickness of a thinner ONO layer to be achieved. Further, the physical thickness of the intergate dielectric layer can be reduced by using atomic layer deposition (ALD) for depositing the high-K material for the intergate dielectric layer(s). Additionally, ALD ensures the deposition of the high-K material with precise uniformity, thickness and abrupt atomic interfaces. For example, an Al2O3 layer with a physical thickness of 10 angstroms (xc3x85) (1 nm) can be deposited using ALD such that the variation in thickness is less than about 0.5 angstroms (xc3x85) (0.05 nm) to about less than 0.1 angstroms (xc3x85) (0.01 nm) across a 200-mm wafer. Thus, an intergate dielectric layer of Al2O3 having an electrical equivalent thickness of 1 angstrom (xc3x85) (0.1 nm) of SiO2 would have a physical thickness of about 10 angstroms (xc3x85) (1 nm). Alternatively, the intergate dielectric layer may be formed of more than one layer. For example, a nitride layer with a K of 7.8 and a physical thickness of 50 angstroms (xc3x85) (5 nm) is substantially electrically equivalent to a SiO2 layer having a physical thickness of 25 angstroms (xc3x85) (2.5 nm). Thus, an intergate dielectric layer including two Al2O3 layers of 10 angstroms (xc3x85) (1 nm) (each) and a nitride layer of 50 angstroms (xc3x85) (5 nm) would have an electrical equivalent thickness of 27 angstroms (xc3x85) (2.7 nm) of SiO2, but have a physical thickness of 70 angstroms (xc3x85) (7 nm). Therefore, in one embodiment, the ONO layer can be replaced with an electrically thin high-K intergate layer that is also a physically thinner layer. It should be understood by those skilled in the art that the ONO layer, in an alternative embodiment, could be replaced with an electrically thin high-K intergate layer that is physically thicker than a conventional ONO of the same electrical equivalent thickness.
According to one aspect of the invention, the invention is a semiconductor device formed on a semiconductor substrate. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.
According to another aspect of the invention, the invention is a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer wherein the floating gate defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate wherein the intergate dielectric layer has a dielectric constant greater than SiO2 and the intergate dielectric layer is deposited by atomic layer deposition (ALD).
According to another aspect of the invention, the invention is a method of fabricating a semiconductor device formed on a semiconductor substrate having an active region. The method includes the step of forming a gate dielectric layer on the semiconductor substrate. Further, the method includes the step of forming a source and a drain within the active region. The method fighter includes the steps of forming a floating gate on the gate dielectric layer wherein the floating gate defines a channel interposed between the source and drain and of forming a control gate above the floating gate. Additionally, the method includes the step of forming an intergate dielectric layer by atomic layer deposition (ALD) interposed between the floating gate and the control gate. The step of forming the intergate dielectric layer has a dielectric constant greater than SiO2.
A reduction in the physical thickness of one or more of the SiO2 layers of the intergate dielectric layer may adversely affect the performance of the finished device, such as the data retention of the FLASH memory device, and increase the difficulty of scaling the device for miniaturization and reduction of power consumption. The replacement of one or more of the SiO2 layers of the ONO layer with a high-K material using ALD techniques allows further electrical scaling of the device. Additionally, the ALD techniques allow for the layer(s) to be manufactured at reduced thicknesses with high degrees of quality, precision, uniformity and thicknesses. Thus, the reliability, the quality, the speed, and the lifetime of the device are increased.